1. Field of the Invention
The present invention relates to a clock synchronizing circuit and more particularly to a clock synchronizing circuit applicable to a demodulating device of the type executing orthogonal modulation by digital signal processing.
2. Description of the Background Art
Recent LSI (Large Scale Integrated circuit) technologies have made it possible to apply a demodulating device of the type executing digital signal processing to a QAM (Quadrature Amplitude Modulation) high-speed communication system featuring a modulation speed of 10 MHz or above. A digital demodulating device is advantageous over an analog demodulating device in that it is free from time-varying factors and irregular characteristics. Further, a digital demodulating device can be integrated and needs no adjustment.
However, the problem with the demodulating device for QAM application is that two channels are not fully coincident as to the electric length of a baseband circuit due to, e.g., the irregular delays of analog parts. Therefore, even if sampling clocks on two channels are coincident, not both of the sampling timings of two channels are always optimal. For example, it is likely that clock control executed to optimize a P channel side shifts a Q channel side or that clock phase control executed to select the mean value of the P and Q channel sides shifts both of the P and Q channel sides. Such a shift or error is not negligible when modulation speed is high. Moreover, in the case of a quasi-synchronous detection type of demodulator, an equalizer cannot cancel the shift and causes a BER (Bit Error Rate) characteristic to be degraded. This problem is particularly serious when the number of modulation levels is great.
Technologies relating to the present invention are disclosed in, e.g., Japanese Patent Laid-Open Publication Nos. 10-224238, 10-322405, 11-103327, and 11-177644.
It is an object of the present invention to provide a clock synchronizing circuit capable of automatically compensating for a difference in electric length between baseband circuits on two channels to thereby obviate the degradation of the BER characteristic.
In accordance with the present invention, a clock synchronizing circuit includes a first AD (Analog-to-Digital) converter for converting a first-channel baseband signal, which is subjected to orthogonal detection together with a second-channel baseband signal, to a first digital signal. A second AD converter converts the second-channel baseband signal to a second digital signal. A controller controls the sampling phase of the second AD converter on the basis of the first digital signal. A detector detects a shift of the sampling phase of the second digital signal relative to the first channel. An interpolator interpolates the second digital signal in accordance with a coefficient based on the shift of the sampling phase detected by the detector.